IMPLEMENTATION OF UNIVERSAL ASYNCHOONOUS TRANSMITTER RECIEVER (UART) USING FPGA TECHNOLOGY (Record no. 78348)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00335nam a2200121Ia 4500 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 PAL |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | PAL, VIJAY |
| 245 ## - TITLE STATEMENT | |
| Title | IMPLEMENTATION OF UNIVERSAL ASYNCHOONOUS TRANSMITTER RECIEVER (UART) USING FPGA TECHNOLOGY |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher, distributor, etc | 2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent/Pages | 69 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Elec. Thesis & Dissertation |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Barcode | Date last seen | Bill Date | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Delhi Technological University | Delhi Technological University | 25/08/2015 | 621.3815 PAL | TD271 | 25/07/2016 | 25/07/2016 | Elec. Thesis & Dissertation |